Advances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in shrinking digital logic circuits and increases in the probability of soft-errors. Although many modern microprocessor's large memory arrays, such as caches or register files, may be protected by error detection and correction (EDAC) schemes, chip-level soft error rates (SER) tend to be dominated by the error rates of latches and flip-flops in application-specific integrated circuits (ASICS), microprocessors, and field-programmable gate arrays (FPGAs). As chip-level logic SER performance worsens with scale, there is a need to increase performance-efficient hardened latch and flip-flop designs to meet Failure-In-Time (FIT) requirements without adding significantly to the space and monetary costs to do so.
Scaling is known to decrease both power supply voltage Vcc and capacitance C. In latch and/or flip-flop circuits, the critical charge Qcrit is the minimum amount of electron charge disturbance needed to cause a change in the logic level of a portion of a circuit. As Qcrit can be calculated according to Equation 1, Qcrit may be expected to decrease as a result of scaling the Vcc and/or the capacitance C.Qcrit∝C×Vdd  Equation 1
The SER may be calculated based on the sensitive drain area Adiff, the collected charge Qcoll, and Qcrit. Accordingly, SER is based on the capacitance C and the Voltage Vcc.
                    SER        ∝                              A            diff                    ×                      e                          -                              Qcrit                Qcoll                                                                        Equation        ⁢                                  ⁢        2            
Existing hardening solutions, like dual interlocked storage cell (DICE) carry a large area and performance overhead. Moreover, solutions like triple modular redundancy (TMR) require custom place and route (PnR) flows and cannot be used in ASICS. Accordingly, there is a need to harden circuits to alpha and neutron particles without significantly increasing the area, delay, and power requirements to do so.